Frequency discriminators or frequency demodulators are widely used and are used in frequency synthesizers or as demodulators in frequency modulation receivers.
FIG. 1 shows a delta/sigma frequency discriminator (DSFD) according to the prior art as described in R. Beards, M. Copelend, “An Oversampling Delta-Sigma Frequency Discriminator”, IEEE Trans. On Circuits and Systems II, Vol. 41, Vol. 1, January 1994. The delta/sigma frequency discriminator receives an input signal at an input E1 and a reference clock signal at an input E2. The delta/sigma frequency discriminator (DSFD) determines the frequency of the input signal and outputs a corresponding digital value at its output A. For this purpose, the delta/sigma frequency discriminator (DSFD) according to the prior art as shown in FIG. 1 contains a dual modulus frequency divider which divides the input signal at the signal input E1 at a frequency dividing ratio which can be switched in dependence on the digital output signal. A sampling register samples the divided input signal by means of the reference clock signal for generating the digital output signal. The reference clock signal is generated, for example, by a reference clock generator.
In the delta/sigma frequency discriminator DSFD according to the prior art, a digital output signal is generated which consists of a one-bit datastream. Depending on the logical state of the output signal, the frequency dividing ratio of the frequency divider is switched between a first frequency dividing ratio N and a second frequency dividing ratio N+L, where N, L are two suitable integer values. The delta/sigma frequency discriminator measures the frequency Fv of the input signal in comparison with the frequency FR of the reference clock signal.
The following applies:
                              Mean          ⁢                                          ⁢                      value            ⁡                          [              C              ]                                      =                                            F              v                                                      (                                  N                  +                  L                                )                            /              2                                -                      F            R                                              (        I        )            where C represents the digital output signal.
L is typically selected to be much smaller than N, for example N=92 and L=4. The digital datastream C at the output of the delta/sigma frequency discriminator DSFD represents the frequency difference between the input signal, which has a relatively high frequency, and the low-frequency reference clock signal. The reference clock signal is generated by a reference clock generator, for example a crystal oscillator. The delta/sigma frequency discriminator DSFD measures the frequency Fv of the input signal. The output datastream exhibits a first-order quantization noise (+20 DB/DEC).
However, the delta/sigma frequency discriminator (DSFD) according to the prior art as shown in FIG. 1 has the disadvantage that in a frequent case when the frequency Fv of the input signal is constant, strong interfering modulation tones occur in the signal spectrum of the digital output signal (C). The same problem occurs in first-order delta/sigma modulators. The base frequency of the interfering modulation tones depends on the difference between the frequency Fv of the input signal and the frequency FR of the reference clock signal. It can happen that the interfering modulation tones occur within the low frequency band so that they can no longer be eliminated by a subsequent digital low-pass filtering. This leads to a considerable deterioration in the performance of the data processing system.
It has been attempted, therefore, to eliminate the interfering modulation tones by increasing the order of the delta/sigma frequency discriminator. For example, second- and third-order delta/sigma frequency discriminators (DSFD) have been proposed, for example in I. Galton, “A Practical Second Order Delta Sigma Frequency to Digital Converter”, IEEE Inter. Symposium on Circuits and Systems, 1995, and M. Hovin et al., “Novel Second Order Delta-Sigma Modulator Frequency to Digital Converter”, Electronic Letters, Vol. 31, No. 2, January 1995 or T. Riley et al., “A two-loop Third Order Multistage Delta-Sigma Frequency to Digital Converter”, IEEE Intern. Symposium on Circuits and Systems, 1998. However, these delta/sigma frequency discriminators (DSFD) need analog circuit sections for implementing integrators in the feedback loop or providing charge pumps. Although the proposed delta/sigma frequency discriminators partially attenuate or suppress the interfering modulation tones at the output, they can only be implemented with complex circuitry, especially due to the analog circuit sections.